1. Field of the Invention
The present invention is related to the field of electronics. In particular, the present invention is related to a method and apparatus for controlling memory accesses.
2. Description of the Related Art
Dynamic Random Access Memories (DRAMs) have memory precharge, activate, read, and write operations. In particular, a memory controller that addresses a bank of memory must first precharge the memory bank, then the addressed page within the bank must be activated before the addressed column in that page is accessed (read or written). A xe2x80x9cDRAM page openxe2x80x9d or a xe2x80x9cpage hitxe2x80x9d indicates the memory being accessed has already been precharged and activated, and data may be read or written from the page without having to precharge or activate the memory during each memory access. When a xe2x80x9cpage miss occursxe2x80x9d (i.e., data is accessed from a page in memory other than from the page that is open), the open page must be written back to the DRAM chip from the sense amps. Next, the new memory page has to first be precharged and activated before being accessed. Writing the old page to DRAM, and precharging and activating the new DRAM pages takes time and slows down memory accesses resulting in an inefficient use of the memory bus (reduced bandwidth) and a loss in performance of an apparatus (e.g., a computer) employing DRAM.
FIG. 1 illustrates a front side bus (FSB) controller that schedules memory accesses according to a prior art embodiment. As illustrated in FIG. 1, the FSB controller 105 includes a FSB scheduler 125 that schedules accesses (reads and writes) from a processor 110 to DRAM 120 via a FSB access queue 130. The FSB controller is coupled to processor 110 via a L2 miss request bus and to memory controller 115 via a front side bus. The memory controller 115 is coupled to DRAM 120 via a memory bus. Processor 110 comprises an out-of-order core 135 and a hardware prefetcher (HWP) 140. The out-of-order core 135 uses a pipelining technique wherein multiple instructions are overlapped in execution in an effort to improve the overall performance of the processor. The HWP prefetches data needed by execution units in the out-of-order core from DRAM.
The FSB controller 105 and in particular the FSB scheduler 125 schedules DRAM accesses from the processor 110 (i.e., from the out-of-order core and from the HWP) based upon the relative age of the instructions that caused the access (i.e., a load or store resulting in a request for reading or writing data to DRAM). Hence the accesses in the FSB access queue 130 are scheduled to DRAM in program order. In particular, DRAM accesses from the out-of-order core have priority over DRAM accesses from the HWP, and accesses generated by the out-of-order core are scheduled in program order. Thus, the FSB controller minimizes the DRAM access latency by first scheduling the accesses associated with the oldest instruction in the FSB access queue. However, scheduling DRAM accesses based upon minimizing the latency of DRAM accesses is not always the optimum solution, as successive DRAM accesses may not always access open DRAM pages. Accesses from a closed DRAM page involve writing the currently open page to DRAM, and precharging and activating a new DRAM page. Thus, accessing a closed DRAM page takes time and slows down memory accesses, thereby rendering the processor""s DRAM bus inefficient.